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MC33157 Half Bridge Controller and Driver for Industrial Linear Tubes
The MC33157 includes the oscillator circuit and two output channels to control a half-bridge power stage. One of the channels is ground-referenced. The second one is floating to provide a bootstrap operation for the high side switch.
Dedicated Driver for Industrial Linear Tubes http://onsemi.com
* Main oscillator is current controlled, making it easy to set up by a * *
single external resistor. On top of that, such a feature is useful to implement a dimming function by frequency shift. Filament pre-heating time control built-in. The strike sequence is controllable by external passive components, the resonnant frequency being independently adjustable. This frequency can be made different from the pre-heating and the steady state values. A frequency sweep between two defined values makes this IC suitable for any series resonnant topologies. Dedicated internal comparator provides an easy lamp strike detection implementation. Digital RESET pin provides a fast reset of the system (less than 10s). Both output MOSFET are set to "OFF" state when RESET is zero. Adjustable dead time makes the product suitable for any snubber capacitor and size of MOSFET used as power switches. Designed to be used with standard setting capacitors 470nF. A voltage reference, derived from the internal bandgap, is provided for external usage. This voltage is 100% trimmed at probe level yielding a 2% tolerance over the temperature range.
R ENDSWP C SWEEP R PH C PH 5 +Vref 15 V PREHEAT & STRIKE CONTROL COMPARATOR UVLO BAND GAP REFERENCE +Vref (+7 V) DT adjust 8 Latch Strike 9 Detection 10 Vth Q C Clear RESET INHIBIT ENABLE Dead Time CONTROL LOGIC Strike Detection LOW SIDE BUFFER R Iph Ifstrike Iop +Vref +Vref LEVEL SHIFTER HIGH SIDE BUFFER 16 VHS 15 VHO 14 VOUT 13 NC 12 VLO 11 GND Iph 3 C OP 6 7 R OP ICO 2 +Vref
16 1 SO-16L DW SUFFIX CASE 751G
* * * * *
PIN CONNECTIONS AND MARKING DIAGRAM
VDD +Vref CPH RPH CSWEEP COP ICO DTA 1 2 3 4 5 6 7 8 MC33157DW AWLYYWW (Top View) 16 VHS 15 VHO 14 VOUT
12 VLO 11 GND 10 RESET 9 SD
V DD 1 4
AWL = Manufacturing Code YYWW = Date Code
R
ORDERING INFORMATION
Device MC33157DW Package Plastic SO-16L Shipping 47 Units / Rail
R
(c) Semiconductor Components Industries, LLC, 1999
1
November, 1999 - Rev. 1
Publication Order Number: MC33157/D
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ELECTRICAL CHARACTERISTICS (VDD = 14V. All parameters are specified for -20C to 85C ambient temperature MAXIMUM RATINGS
unless otherwise noted.) OSCILLATOR OUTPUT DRIVERS (VLO, VHO) SUPPLY VOLTAGE ICOP over IROP current ratio ICOP discharging current VCOP Low threshold VCOP High threshold System operation programming recommended values Internal Master Clock Duty Cycle Output Max Frequency High Side / Low Side fall time @ COUT = 2 nF High Side / Low Side rise time @ COUT = 2 nF Low Side VDSON @ Sink current = 300 mA High Side VDSON @ Source current = 250 mA Quiescent Current at No Load @ VDD > UVON Standby Current at No Load @ VDD < UVOFF Supply Current (Note 2) Clamp Voltage @ ICLAMP = 10 mA Input Threshold Voltage Turn-On Turn-Off Electrostatic Discharge [HBMI] Storage Temperature Range Supply Voltage (Note 1) Maximum Power Dissipation @ TA = 50C Thermal Resistance Junction-to-Air Operating Junction Temperature Max VHO/VLO Allowable Slew Rate Max VHS Allowable Slew Rate Low Side Output Voltage Range High Side Output Voltage Range Differential Max Voltage VHS - VOUT High Side Max Voltage Characteristic Rating
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MC33157
2 ROP RPH RENDSWEEP RDTA COP VCLAMP ISTDBY Symbol VDS(N) VDS(P) UVON UVOFF dVHO/dt, dVLO/dt fOSC DC IQ IS tr tf dVHS/dt Symbol
DVHS
VDD PD RJA TJ Tstg
VHO
ESD
VHS
VLO
Min
68 68 68 10 100
11 8.0
15
- - - - - - -
VOUT-0.3 to VHS+0.3
Typ
400 880 880 12 8.5 2.8 4.2 2.5 1.5 50 35 40 12 16
2.0
16 600 140 -40 to +150
-65 to +150
-0.3 to +16
Value
600
10
10
2.0
16
560 560 2200 250 560
1500
1500
16.5
12.8 9.0
Max
250
- - - - -
Unit
kHz
V mW C/W C
mV
mV
mA
mA
mA
V/ns
V/ns
Unit
kW kW kW kW pF
A ns ns % V V V V V
kV C V V V V
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RESET maximum negative voltage RESET maximum voltage RESET input current @ low voltage RESET input current @ high voltage RESET low voltage RESET high voltage Strike detect minimum pulse width Maximum strike detect voltage negative input Maximum current on strike detect input @ Low level Maximum voltage on strike detect @ Regulation level Maximum current on strike detect input @ Regulation level Strike detect low voltage threshold Strike detect high voltage threshold VTHSDLO VTHSDHI VSDNEG RSTLO VSDHI RSTHI SDPW ISDLO ISDHI 1.6 50 - - - - - - - - - - - 3.75 -20 -20 100 1.8 1.8 4.0 - - - - - - -0.3 -0.3 7.0 2.2 7.0 10 10 - - - - - - A A nA nA ns V V V V V V V V
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ELECTRICAL CHARACTERISTICS (continued) (VDD = 14V. All parameters are specified for -20C to 85C ambient temperature
unless otherwise noted.) INPUT VOLTAGE REFERENCE TIMING Total VREF variation over Line, Temperature, Load Maximum load current Load regulation @ ILOAD = 500 A to 5 mA Line regulation @ ILOAD = 500 A, TJ = 25C Voltage reference @ ILOAD = 500 A, TJ = 25C Dead time tolerance Dead time adjust resistance (Recommended range) Dead time: externally adjustable by Rdt Strike sequence restart blanking time with CPH = 470nF CPH charging current ratio Strike sequence recycling time with CPH = 0.47 F Filament preheat time with CPH = 0.47 F Preheat timing capacitor pulsed charging current (Duty Cycle=1/16) Characteristic
NOTES: (1) Since this device has a built-in zener, one cannot use a low impedance supply to drive this pin. Having a current limit mode by external means is mandatory. (2) Test Conditions: COUT = 2.2 nF, f = 100 kHz, VDD = 15V.
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MC33157
3 IREFMAX Symbol
DVREF DVREF
VREF dtTol ItPH tPH tSK Rdt tbk dt
VREF
6.85 Min 0.3 10 14 - - - - - - - -
1/16
Typ
10
125
7.0 7.0 2.0 10 10 10 16 - - -
7.15 220 2.5 25 17 - - - - - - -
Max
Unit
mA mV mV ms ms kW A s % V s
V
MC33157
PIN FUNCTION DESCRIPTION
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1 VDD Supply voltage input This pin provides the DC supply to the circuit. The voltage is internally clamped by a zener connected to the ground. It is NOT allowed to use a DC low impedance power supply to feed this pin, but limiting the current by an external resistor is mandatory. It is recommended to damp this pin to ground by an electrolytic capacitor connected close to pin 1. This pin provides a +7V voltage reference derived from the internal bandgap. The +Vref can supply up to 25 mA and shall be decoupled to ground by a 220nF ceramic capacitor 2 +Vref Voltage reference output 3 CPH Preheat timing capacitor This capacitor sets two timings: filaments preheat time (tPH) and strike sequence recycle time (tSK). It is charged with a constant current and cares must be observed to minimize the leakage current at this pin to get the expected timing. Typically, a 0.47 F capacitor will give a 2 seconds pre-heating time and a 125 ms strike sequence recycle time. (See details given by figure 9) The RPH resistor together with RENDSWEEP and COP defines the frequency used to preheat the filaments (fPH = f1). RENDSWEEP defines the strike frequency (fENDSWEEP = f2). During the sweep timing, the frequency will sweep from the high pre-heating f1 to the low strike f2 values. Normally, f1 is far from the LC resonance but f2 is close enough to generate the high voltage across the fluorescent tube. (See details given by figure 9) This timing define the sweep time from f1 to f2. Since the timing capacitor is charged with a low constant current, cares must be observed to minimize the leakage current at this pin to get the expected timing. Since this capacitor is charged through resistor RPH, the voltage rises according to an exponential and the frequency shifts with the same law. 4 RPH Preheat and Strike frequencies adjustment resistors 5 CSWEEP Frequency sweep timing capacitor Oscillator capacitor 6 COP This pin defines the steady state operation frequency (f3 = fOP) of the controller. Since this timing capacitor is charged with a low constant current, cares must be observed to minimize the leakage current at this pin to get the expected frequency. Film type capacitor are recommended (polycarbonate). 7 ICO Steady state operating frequency adjustment current input Dead Time Adjust Since the circuit uses a Current Controlled Oscillator (ICO), the current forced into this pin will control the operating frequency. The allowable current range is from 1 A to 500 A. The +Vref output can be used to provide the voltage across ROP. An auxiliary voltage source can be used to implement a dimming function. 8 9 DTA SD This pin provides an access to the internal timing system to adjust the dead time between the gate drive of the High and Low power switches connected, respectively, to pin VHO and VLO. Strike detection input This pin drives a comparator, with an internal fixed reference, and acknowledges the tube strike. When a negative going slope (across the internal reference) is detected, the system considers the lamp has struck and the oscillator jumps from the present frequency value, which is within the window defined by RPH and RENDSWEEP to the steady state value defined by ROP. If no negative going slope is detected on this pin, the system will repeat the sweep and strike sequence four times, then stops. The circuit will re-start from either a RESET, or by pulling +VDD to ground. The input signal can be either a logic level or an analog voltage ramping up from zero to +Vref followed by a negative going slope to zero. In any case, the positive pulse width must be 1 s minimum. The pcb layout must be designed to minimize the noise at this pin. (See details given by figures 8, 9, & 10) Forcing a logic zero to this pin (HCMOS low level) will reset the circuit, initializing a frequency sweep and lamp strike sequence. The master reset does not include the pre-heating timing. The minimum pulse width requested is 10s to guarantee a reset state. However, this pin has no built in filtering and a shorter pulse may initialize a reset sequence: it is the responsibility of the designer to make sure that no noise or parasitic pulse are developed at the RESET input. A full re-start of the sequence, including the pre-heating time, can be initialized by pulling the +VDD pin to ground. In this case, +VDD and RESET must be simultaneously released to a high state. When RESET is asserted low (active) both outputs MOS are biased in the off condition. An internal 20A pull up current forces the pin to logic one, allowing the designer to left this pin open if the RESET function is not used. In order to avoid any uncontrolled state of the output drivers, it is recommended to set up a 10ms low level at pin 10. The reset is activated in less than 10 microsecond, but releasing this pin while the Vcc supply is high (above 300V) can generate a random operation, depending upon the dv/dt coming from the power supply. 10 RESET Master reset input
Pin
Symbol
Function
Description
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MC33157
PIN FUNCTION DESCRIPTION (continued)
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11 GND Ground (zero voltage reference) Since high and fast currents circulate in the circuit, it is mandatory to build a single ground point in the system. This pin provides the VGS to drive the Low side power MOSFET. 12 13 14 VLO NC Low side driver output Not Connected VOUT High side common point / Half bridge output This pin is connected to the output of the half bridge and is referenced for the High side switch. 15 16 VHO VHS High side driver output High voltage boost supply This pin provides the VGS to drive the High side power MOSFET. The gate drive of the High side switch is derived from this voltage.
Pin
Symbol
Function
Description
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5
MC33157
+Vref
6 COP External
2K
Internal Circuits
10 V ESD
10 V ESD
Figure 1. PIN 6 COP INPUT
+Vref
IPH
ISWP (8 UA) ph/swp Switch
CAN'T READ
2K
3
Iblanking (200 uA)
10 V ESD
10 V ESD
CPH (external)
Figure 2. PIN 3 CPH INPUT
+Vref
Internal Circuits
5V 0V
10 10 V ESD
2K 10 V ESD
Figure 3. PIN 10 RESET
+Vref
4V
0.0 V
Internal Circuits
9 10 V ESD
2K 10 V ESD Hysteresis Switch
Figure 4. PIN 9 SD http://onsemi.com
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MC33157
+Vref
8 I 2K 8 RDTA (external) 10 V ESD 10 V ESD
1 I/8 Internal Circuits
Figure 5. PIN 8 DTA
+Vref 10 V ESD I 2K 7 10 V ESD 10 V ESD 6 2I COP (external) 1 kW (internal) 1 kW (internal)
2 ROP (external)
Figure 6. PIN ICO
+Vref 2 ph/swp switch 2K 10 V ESD 10 V ESD CSWP (external) 5 RPH (external) 4 RENDSWEEP (external) I 10 V ESD 10 V ESD 6 2I COP (external) 10 V ESD
2K
1 kW (internal)
1 kW (internal)
Figure 7. PIN 2, 4 & 5 Vref, RPH & CSWP
V T
w1 ms
SDLOVth 3.75 V typ
SD max SDHIVth 4 V typ Internal Hysterisis t The Strike Detect is acknowledged as soon as the input voltage drops below SDLOVth. It is not necessary to pull the input voltage to zero volt or to a negative bias SDNEG max
Figure 8. STRIKE DETECTION http://onsemi.com
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MC33157
Rise time V DD U VON 9.2 V typ U VLO 3.8 V typ
wlms
U VLO RESET
7.0 V typ V ref V CPH (PREHEAT) Frequency SWEEP STRIKE DETECTION tph
t
w1 m s
STRIKE
1 RESET 0 Output Frequency OFF STATE status
FSwp FSwp
F1
F2
F3
OFF STATE
F1
F2
F3 time
f1 = fPH, preheating frequency adjusted by RPH and RENDSWEEP f2 = fENDSWEEP, end of sweep frequency, adjusted by RENDSWEEP (pin 2). In any case f1 f3 = fOP, operating frequency controlled by the ICO current (pin 7) and capacitor COP tPH = (CPH * 2/3 * Vref) / ( * ItPH) "OFF" state: High side switch OFF, Low side switch ON
w f2
Figure 9. TIMING DIAGRAM (Normal startup sequence and UVLO reset)
w10 ms
1 RESET 0 +V ref V CSWP STRIKE DETECTION SD HIGH SD LOW V CSWP repeats indefinitely No further logic action activated
Output Frequency status
F3 Previous On state
OFF STATE
FSweep
F3 time
When RESET pin is released to a logic one, the system jumps to the preheat frequency as defined by RPH, then executes a frequency sweep down to fENDSWEEP, as defined by RENDSWEEP, and waits until a strike detection signal is applied to pin 9. There is no preheating timing performed after a reset coming from pin 10. RESET logic level is CMOS compatible. Note: Strike detection lever can be either digital - CMOS or analog as depicted here above, as long as the signal fulfills the SDHIGH and SDLOW values and timing. OFF STATE: both output MOSFET are biased in the off condition.
Figure 10. TIMING DIAGRAM (External reset)
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MC33157
1 RESET 0 End of preheating sequence Blanking 10 ms typ @ C PH = 470 nF Blanking
+V ref V CSWP
Last restrike valid cycle
tF V
t FEND SD HIGH SD LOW
w+Vref
t SK
STRIKE DETECTION
Output Frequency status
FSweep
F2 F1 FSweep F2 F1 FSweep F2 F1 FSweep
F2
F3 time
tSF: Sweep Frequency time. This time is given by the RC network built with CSWEEP and RPH. tSK: Sweep sequence recycle time. This time is derived by integrating a constant DC current in capacitor CPH. There is a fixed ratio ( ) between the preheating time tPH and strike sequence recycle time tSK. tfEND: Time during which f = (fENDSWP). This time is equal to tSK - tSF. The controller repeats the fSWEEP and the strike sequence until there is a STRIKE signal coming from the external circuit, or until FOUR sequences have been counted. Following a non strike situation, the controller goes in a full STOP and can be reinitialized by either pulling the VDD pin 1 to ground or by forcing a low to the RESET pin 9. The controller assumes the lamp has struck when a negative going transient is applied on the STRIKE detection pin 10. On the other hand, in order to avoid false strike information, the controller force a blank time between the end of tSWEEP and the start of the next sequence.
Figure 11. TIMING DIAGRAM (no strike conditions)
5 4.5
I = V/ [(R2 + (Lw - 1/Cw)2]
4
I = V/ [(R2 + (Lw)2]
3.5
Z @ RLCF
Z = Lw Current (A)
3 2.5 2 1.5 1 0.5 0 13000 17000 21000 25000 29000 33000 37000 41000 45000 49000 53000 57000 61000 65000 69000 73000 77000 93000 81000 85000 89000 97000 5000 9000
Frequency (F) Figure 12. OUTPUT = f (freq) @ Lc = 1.5 mH, Cs = 6.8 nF
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MC33157
+400 V C3 C4 R4 7 C2 C1 R2 IC 6 0 C OP 3 C PH 4 R PH R1 2 1 D1 10 m F/25 V R3 R9 MUR160 100 nF 16 V HS V HO 100 nF/400 V C9 100 nF/400 V
15 Ns 14 330 pF Q2 MTP6N60E Np R6 T1
U1 MC33157
V OUT
C12
C6 R5
5 8
C SWP D TA
V LO
12
D3
1N4148
100 nF
RESET 10
GND 11
SD 9
Typical Values for FPH = 70 kHz, FOP = 45 kHz, tPH = 2 s, tSWEEP = 125 ms T1 Np = R1 390 kW C1 470 nF/25 V/Polyester Ns = R2 62 kW C2 470 pF/2%/50 ppm Lp = 150 mH R3 100 kW - 0.5 W C3 10 mF/25 V/Electrolytic Q1 MTP6N60E R4 100 kW C4 220 nF/Polyester Q2 MTP6N60E R5 82 KW C5 100 nF/63 V/Polyester D1 MUR160RL R6 1 MW C6 220 nF/25 V/Polyester D2 MUR120RL R7 68 KW C7 6.8 nF/5%/1000 V D3 1N4148 R8 68 kW C8 100 nF/400 V/Polyester U1 MC33157 R9 22 W C9 100 nF/400 V/Polyester C10 22 mF/450 V/Electrolytic C11 100 nF/25 V/Polyester C12 330 pF/500 V/Polyester TO SEE: AN1682 (Using the MC33157 Electronic Ballast Controller)
Figure 13. Typical Application Schematic Diagram
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10
C11
R8
R7
C8
C10
C5
C7
+V REF V DD
Q1 MTP6N60E
22 m F/450 V
MC33157
PACKAGE DIMENSIONS SO-16L DW SUFFIX PLASTIC PACKAGE CASE 751G-03 ISSUE B
D
16 M 9
A
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 10.15 10.45 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
B
1
8
16X
B TA
S
B B
S
h X 45 _
M
8X
0.25
E
0.25
M
A1
14X
e
SEATING PLANE
DIM A A1 B C D E e H h L
A
L
T
C
q
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MC33157
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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MC33157/D

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